The present invention generally relates to a method for forming an electrical conductor in an electronic structure and more particularly, relates to a method for forming an electrical conductor that contains up to 2 atomic % of an impurity element surrounded by a liner that contains Ti.
The technology of making metal conductors to provide for vias, lines and other recesses in semiconductor chip structures, flat panel displays and package applications has been developed in the past decade. For instance, in developing interconnection technology for very-large-scale-integrated (VLSI) structures, aluminum has been utilized as the primary metal source for contacts and interconnects in semiconductor regions or devices located on a single substrate. Aluminum has been the material of choice because of its low cost, good ohmic contact and high conductivity. However, pure aluminum thin-film conductors have undesirable properties such as a low melting point which limits its use to low temperature processing and possible diffusion into the silicon during annealing which leads to contact and junction failure, and poor electromigration resistance. Consequently, a number of aluminum alloys have been developed which provided advantages over pure aluminum.
Recently developed USLI technology has placed more stringent demands on the requirements due to the extremely high circuit densities and faster operating speeds required of such devices. This leads to higher current densities in increasingly smaller conductor lines. As a result, higher conductance wiring is desired which requires either larger cross-section wires for aluminum alloy conductors or a different wiring material that has a higher conductance. The obvious choice in the industry is to develop the latter which includes pure copper for its desirable high conductivity.
In the formation of ULSI interconnection structures such as vias and lines, copper can be deposited into such recesses to interconnect semiconductor regions or devices located on the same substrate. However, copper is known to have problems in semiconductor devices. The electromigration phenomenon occurs when the superposition of an electric field onto random thermal diffusion in a metallic solid causes a net drift of atoms in the direction of electron flow. Any diffusion of copper atoms into the silicon substrate can cause device failure. In addition, pure copper does not adhere well to oxygen-containing dielectric material such as silicon dioxide and polyimide. To fully utilize copper in interconnection technology, the adhesion properties of copper must also be improved.
The back-end-of-line (BEOL) copper metallurgy further requires liners that are multi-functional, which includes the adhesion to dielectric, the diffusion barrier to the copper, the lowest resistance for contacts and line redundancy, and the reliability of copper. One of the presently used liner technology in the industry is a layered TaN/Ta system for a copper conductor. The TaN layer is required for adhesion and conversion of Ta to the low resistance allotropic alpha phase. The Ta layer provides a diffusion barrier, redundancy and adhesion to copper.
It is therefore an object of the present invention to provide a liner for an electrical conductor in an electronic structure that does not have the drawbacks; or shortcomings of conventional liner materials.
It is another object of present invention to provide a liner for electrical conductors in an electronic structure that provides improved electromigration resistance.
It is a further object of the present invention to provide a liner for electrical conductors in an electronic structure that contains Ti.
It is another further object of the present invention to provide a liner for Cu conductors that has improved reliability and electromigration resistance.
It is still another object of the present invention to provide a liner for a Cu conductor in a semiconductor structure that is compatible with a single damascene or dual damascene process.
It is yet another object of the present invention to provide an electrical conductor in an electronic structure that includes a conductor body formed of an alloy containing up to 2 atomic % of an element selected from Ti, Zr, In, Sn and Hf.
It is still another further object of the present invention to provide a Cu conductor in a semiconductor structure that has an abutting liner formed of a material containing Ta, W, Ti, Nb, and V.
In accordance with the present invention, a conductor in an electronic structure that includes a conductor body and a liner is disclosed.
In a preferred embodiment, a conductor in an electronic structure is provided which includes a conductor formed of an alloy including between abut 0.001 atomic % and about 2 atomic % of an element selected from the group consisting of Ti, Zr, In, Sn, and Hf, and a liner abutting the conductor body formed of an alloy that includes Ta, W, Ti, Nb and V.
In the conductor formed in an electronic structure, the conductor body may further include Cu or Al. The conductor body may further include Cu and Ti, the liner may further include between about 10 atomic % and about 60 atomic % Ta. The conductor body may further include Al and Ti, or the liner may include between about 10 atomic % and about 90 atomic % of Ti. The liner may further include a bi-layer formed of Ta1xe2x88x92XNy and Ta1xe2x88x92X, respectively. The conductor may further be an interconnect in a single damascene structure, or in a dual damascene structure. The conductor body may further include between about 0.001 atomic % and about 2 atomic % Ti, the liner may further include not less than 20 atomic % Ti.
The present invention is further directed to a liner for a semiconductor interconnect that is formed of a material selected from the group consisting of Ti, Hf, In, Sn, Zr and alloys thereof, TiCu3, Ta1xe2x88x92XTix, Ta1xe2x88x92XHfx, Ta1xe2x88x92X Inx, Ta1xe2x88x92X Snx, Ta1xe2x88x92x Zrx and mixtures thereof.
In the liner for a semiconductor interconnect, the material for forming the interconnect may be Ta1xe2x88x92x Tix. When the liner abuts a semiconductor interconnect is formed of Cu or Cu alloy, x=10xcx9c60 atomic %. When the liner abuts a semiconductor interconnect is formed of Al or Al alloy, x=10xcx9c90 atomic %. The liner may further include a bi-layer structure of Ta1xe2x88x92x TixNy and Ta1xe2x88x92X Tix.
The present invention is further directed to a method for forming an electronic structure that can be carried out by the operating steps of first forming an opening in a pre-processed electronic substrate, then depositing into the opening a liner of a material selected from the group consisting of Ti, Hf, In, Sn, Zr and alloys thereof, TiCu3, Ta1xe2x88x92XTix, Ta1xe2x88x92XHfx, Ta1xe2x88x92XInx Ta1xe2x88x92X Snx, Ta1xe2x88x92X Zrx and mixtures thereof, and filling the opening on top of the liner with an alloy includes between about 0.001 atomic % and about 2 atomic % of an element selected from the group consisting of Ti, Zr, Hf, In, and Sn.
The method may further include the step of filling the opening with a Cu alloy or an Al alloy. The method may further include the step of depositing a liner of a bi-layer structure of Ta1xe2x88x92xxe2x88x92yTix Ny and Ta1xe2x88x92xTix. The method can be integrated into a single damascene process, or into a dual damascene process. The method may further include the step of filling the opening with an alloy by a method selected from the group consisting of PVD, CVD, electrodeposition and electroless deposition. The method may further include the atep of depositing the liner in Ta1xe2x88x92XTix and annealing the liner at a temperature not higher than 450xc2x0 C. when x is larger than about 20 atomic %.